Priority encoding logic and circuits

ABSTRACT

In this invention a multi-level hierarchical scalable priority encoding logic and circuits are disclosed. The advantage to make hierarchical priority encoding is to improve the speed and simplify the circuit implementation and make circuit design flexible and scalable. To reduce the time of waiting for previous level priority encoding result, hit signal is generated first in each level to participate next level priority encoding, and it is called Hit Ahead Priority Encoding (HAPE) encoding. The hierarchical priority encoding can be applied to the scalable architecture among the different sub-blocks and can also be applied with in one sub-block.

This application claims the benefit of provisional U.S. Application Ser.No. 60/550,537, entitled “Priority encoding logic and Circuits,” filedMar. 4, 2004, which is incorporated herein by reference in its entiretyfor all purposes.

FIELD OF THE INVENTION

The presentation relates to content addressable memory. In particular,the present invention relates to logic and circuits of priority encodingof match or hit address.

BACKGROUND OF THE INVENTION

In ternary content addressable memory, not every bit in each row arecompared in the searching or comparing process, so some time in onecomparison, there are more than one row matching the input content, itis called multi-hit or match. In multi-hit case, one protocol was madeto select the highest priority address. The logic of selecting thehighest priority address is called priority encoding.

Assume we have {A₀, A₁, . . . A_(n-1), A_(n)} hit signals from thecorresponding addresses and define A₀ has the highest priority and A_(n)has the lowest priority. Assume some of {A₀, A₁, . . . A_(n-1), A_(n)}are logic “1” and all of the others are logic “0”, the priority encodingkeep the highest priority “1” as “1” and convert all the other “1” into“0”. The logic operation of this transform:{A₀, A₁, . . . A_(n-1), A_(n)}

{h₀, h₁, . . . h_(n-1), h_(n)}  (1)can logically be expressed as:h₀=A₀h ₁ ={overscore (A)} ₀ *A ₁h ₂ ={overscore (A)} ₀ *{overscore (A)} ₁ *A ₂...h _(n) ={overscore (A)} ₀ *{overscore (A)} ₁ *{overscore (A)} ₂ . . . A_(n-1) *{overscore (A)} _(n)   (2)

Which means only when A₀ to A₁₋₁, are all zero, h_(i)=A_(i), otherwiseno matter A_(i)=0 or 1, h_(i)=0.

After the priority encoding, the hit address with the highest prioritywill be encoded to the binary address.

If the entry N are large, say 1K to 128K or even 1M, the calculation ofpriority logic (2) will take long time if we use serial logic. So wecome out the inventions which will be described in the following.

SUMMERY OF THE INVENTION

In this invention, we propose a multi-level hierarchical scalablepriority encoding. For example we make 8 entry as one group as firstlevel and 8 first level as a second level, total 64 entry. Then we canmake 8 second level as third level, total 512 entry, and so on. Theadvantage to make hierarchical priority encoding is to improve thespeed, and simplify the circuit implementation and make circuit designflexible and scalable.

To reduce the time of waiting for previous level priority encodingresult, we generate the hit signal first in each level to participatenext level priority encoding, and we call it Hit Ahead Priority Encoding(HAPE) encoding.

The hierarchical priority encoding can be applied to the scalablearchitecture among the different sub-blocks and can also be applied within one sub-block.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 is a block diagram of scalable architecture of CAM with manysub-block in accordance with one embodiment of the present invention.

FIG. 2 a is a logic block diagram of hierarchical priority encoding andmatch address binary encoding within one sub-block in accordance withone embodiment of present invention.

FIG. 2 b is the and timing diagram in accordance with FIG. 2 b ofpresent invention.

FIG. 3 is a logic block diagram of hierarchical priority encoding andmatch address binary encoding in higher level or among the differentsub-block and timing diagram in accordance with one embodiment ofpresent invention.

FIG. 4 is the circuit implementation of priority encoding with 8 inputaddress in accordance with one embodiment of present invention.

FIG. 5 is the circuit implementation of the HIT generation logic addressin accordance with one embodiment of present invention.

FIG. 6 is the circuit implementation of binary encoding logic inaccordance with one embodiment of present invention.

FIG. 7 is the circuit implementation of 8 to 1 mux in accordance withone embodiment of present invention.

DETAILED DESCRIPTION OF THE INVENTIONS

To make the priority encoding logic calculation quicker, the entire CAMblock can be divided into 256 block and divided into four quadruple,each quadruple has 8×8=64 block and each block has 8×8=64 entry as shownin FIG. 1 with embodiment 100.

This is just to explain the principle, the entry number of eachsub-block and the number of sub-block can be different. Assume the datapad 110 are equally distributed in four side of the chip. If all of thedata pad 110 are in one side or less than four side, the principle issame.

First step, route all the data signal in each side (only one side aredrawn in the FIG. 1) to the middle point of that side, which is shown asroute 101 a in FIG. 1. Second step, route all the data signal to thecenter of the chip shown as route 102 a in FIG. 1. Third step, in thecenter point send the data to be compared to both left and right side(only right side path 103 a is shown in FIG. 1. Fourth step, send datato each one of the 8 column both upper part and down part shown as 104 ain FIG. 1. Fifth step, the data to be compared are then sent to eachsub-block 120 in each column to perform the comparison with each entryin every sub-block 120. In embedded application, the entry number ofTCAM is not very large. In that case, the data path start from path 104a. If only some selected sub-block are searched or compared, the data tobe compared will only be sent into those sub-block to save powerconsumption. After comparison with each entry inside each sub-block 120,the first level and second level priority encoding and binary encodingare performed which will be explained in details in FIG. 2, then thepriority encoding in each column 130 among 8 sub-block will be performedas third level priority encoding and the hit address are sent outthrough path 104 b. Next step fourth level priority encoding will beperformed among 8 column 130 in each quadruple and the Hit address aresent out through path 103 b. Next step the priority encoding will beperformed in the center of chip among four quadruple and the hit addresswill be sent through path 102 b. Last step the hit address are sent tothe output pad 110 through path 101 b. The priority encoding among upperquadruple and lower part quadruple can be performed together in path 103b.

The priority encoding logic calculation block diagram for each 8×8=64entry sub-block 120 are shown in FIG. 2 a with embodiment 200 a. Each 8entry of 64 entry are grouped together to do hit logic function from 2 h0 to 2 h 7 and generate Hit[0] to Hit[7] in block 201. In the same timeeach 8 entry of 64 entry are performed priority encoding logiccalculation in each block from 2 p 0 to 2 p 7 of embodiment block 202 togenerate P[63:0], then proceed binary encoding from 2 e 0 to 2 e 7 inembodiment block 203 to generate any three bit BA0[2:0] to BA7[2:0]binary address if there is a hit in any 8 bit group. The eight signal ofHit[0] to Hit[7] from block 201 will perform priority encoding in block206 which is logically exact same as the priority encoding in each 8entry group from 2 p 0 to 2 p 7. The Priority Hit Ph[7:0] from Hit[0] toHit[7] will select the 8 to 1 mux 204 and select one three bit binaryaddress from BA0[2:0] to BA7[2:0] and become Add1[2:0]. The priority bitof Hit[0] to Hit[7] is binary encoded in block 207 which is logicallysame as the binary encoding block from 2 e 0 to 2 e 7 to generate theaddress: Add1[5:3]. Add1[5:3] and Add1[2:0] make Add1[5:0]. Hit[0] toHit[7] further perform the logic function in block 2 hh which islogically same as any block 2 h 0 to 2 h 7 and generate the next levelHit1. Both Add1[5:0] and Hit1 will be passed to the next level.

The timing diagram of embodiment 200 a is shown in FIG. 2 b withembodiment 200 b. Assume all the Hit or miss signal from TCAM comparisonA[i] (A[63:0])which is drawn as signal 240 are available in time t₀, thefirst level hit signal Hit[7:0] generated by block 2 h 0 to 2 h 7 aredrawn as 241 which is available at time t₁. In the same time A[63:0] aredivided into eight group and priority encoded by block 2 p 0 to 2 p 7,generating P[0] to P[63] which are drawn as 244 and available at timet₁. The time delay of generating Ph[7:0] which are drawn as 246 and thetime delay of generating.

BA0[2:0] to BA7[2:0] which are drawn as 245 are roughly same and theyare generated in time t₂. So the Binary address Add1[2:0] which aredrawn as 248 are selected by Ph[7:0] from the 8 group address BAO[2:0]to BA7[2:0] through an eight to one MUX 204 without any further delayexcept the delay of MUX itself which is (t₃−t₂), and the addressAdd1[5:3] which are drawn as 247, Add1[2:0] and Add[5:0] which are drawnas 249 are available at time t₃.

So the total delay from A[63:0] available to the output of binary hitaddress Add1[5:0] is about three stage delay(priority 2 p 0, binaryencoding 2 e 0 and 8 to 1 MUX 204), where we call each block(2 p 0, 2 e0 and 204 etc) as one stage. The delay of Hit1 243 is two stage delay.So the output of Hit1 which is available at t₂ which is one stageearlier than the output of binary Hit address Add1[5:0] 249 which isavailable at t₃. Only Hit1 and Add1[5:0] are sent to the next levelpriority encoding. The entire sub-block are abstracted as symbol 208.The timing delay of hit, priority encoding, binary encoding and 8 to 1mux will be analyzed in details.

FIG. 3 is the logic block diagram of priority encoding of higher levelamong the eight group of 64 entry sub-block or among the 8 sub-block inevery column 130 in FIG. 1. The Hit signal Hit1[7:0] which is marked as313 in FIG. 3 are one stage earlier than the binary hit addressAdd10[5:0] to Add17[5:0] which are marked as 314. Eight bit HIT signalof Hit1[7:0] perform priority encoding in block 309, then the priorityhit signal Ph1[7:0] will select Add2[5:0] from the eight input MUX 311.

In the same time Ph1[7:0] are encoded into binary address Add2[8:6] inblock 310. Add2[8:6] and Add2[5:0] make Add2[8:0]. In block 308 eightinput Hit1[7:0] generate Hit2 at time t₃ which is one stage earlier thanBinary hit address Add2[8:0]. From the timing diagram 340 in FIG. 3, thedelay of binary hit address Add1i[5:0] which is signal 314 to Add2[8:0]which is marked as 319 is an 8 to 1 MUX delay which is (t₄−t₃), wherei=0 to 7. In this hierarchical priority design, the delay on each levelis an 8 to 1 MUX delay because the selection signal from the priorityencoding among the hit signals is available one stage earlier and thereis no extra delay to wait for the selection signal.

Another advantage of this hierarchical priority encoding is that thesimplicity of circuit design. We already see that each level shares thesame logic and circuit design. Say, the priority function block 206, 309in each level are same in logic and circuit, which is shown in FIG. 4,embodiment 400.

Embodiment 400 in FIG. 4 is a sample implementation of the prioritylogic equation (2) which can be deduced to equation (3), where n=7.h₀=A₀h ₁ ={overscore (A)} ₀ *A ₁ ={overscore (A ⁰ +)}{double overscore(A)}{overscore ( ₁)}h ₂ ={overscore (A)} ₀ *{overscore (A)} ₁ *A ₂ ={overscore (A ⁰ +A ¹ +A² )}...h _(n) ={overscore (A)} ₀ *{overscore (A)} ₁ *{overscore (A)} ₂ . . .{overscore (A)} _(n-1) *A _(n) ={overscore (A ⁰ +A ¹ . . . +A _(n-1)+)}{double overscore (A _(n))}{overscore ( )}  (3)

The equation (3) is implemented as embodiment 400 in FIG. 4. Each linefrom 4 y 0 to 4 y 7 connect the drains of a few N transistors and eachline 4 y 0 to 4 y 7 is the output of dynamic NOR logic of N transistorconnected to that line. At the beginning of each cycle, the gate inputsignals {overscore (A₀)}₀ to {overscore (A)}₇ and A₀to A₇ of all the Ntransistor from 401 to 436 are set to logic zero which turn off all theN transistors and the enable signal en is set to logic zero which makesall the output of NAND gate 445 to 452 to logic one and then turn allthe output of inverter 453 to 460 into logic zero . The input pch of theP transistors 437 to 444 are set to logic zero and the P transistor 437to 444 are turned on, which make the line 4 y 0 to 4 y 7 connecting toVdd with low impedance and pre-charge the potential level of line 4 y 0to 4 y 7 up to Vdd, then the signal pch is turned into Vdd and turn offthe P transistors 437 to 444 before the TCAM comparison results A₀ to A₇and their complementary {overscore (A)}₀ and {overscore (A)}₇ arrive.The Hit signal among A0 to A7 will be logical “one” at potential Vdd andthe missed signal among A0 to A7 will be logical zero at potentialground. Only the highest priority hit, the output of the NOR gates arelogically high. For example, A₀=0, A₁=0, A₂=Vdd and A₃=Vdd, the highestpriority hit is A₂. The input of N transistor 401 is Vdd and Ntransistor 401 is turned on and the node 4 y 0 is discharged to ground.The input of transistor 402 which is the complementary of A₁ is also Vddand the transistor 402 is ON, the node of 4 y 1 is also discharged toground.

Since A₀=0, A₁=0, A₂=Vdd, {overscore (A)}₂=0, so the inputs oftransistors 404, 405,406 are all zero and the transistor 404,405,406 areall OFF and the node 4 y 2 will not be discharged and will be keptlogically “one” at potential Vdd. Since A₂=Vdd, the inputs oftransistors 408, 413, 419, 426 and 434 will be Vdd and all the node 4 y3, 4 y 4, 4 y 5, 4 y 6 and 4 y 7 will be pulled to ground no matter ifA₃, A₄, A₅, A₆ and A₇ are logically one or zero. The slowest path orworst case is only one input among eight N transistor429,430,431,432,433,434,435 and 436 connected to node 4 y 7 is Vdd andall the others are zero, in that case one transistor need to dischargethe drain parasitic capacitance of eight transistor and the metal wirecapacitance connected to node 4 y 7. The signal en is characterized toturned to Vdd later then node 4 y 7 is discharged in worst case. Theworst case delay of eight input priority encoding is that one Ntransistor discharging the drain parasitic capacitance of eight samesize N transistor down to ground plus the delay of one NAND gate and oneinverter.

The logic of Hit function block 2 h 0, 2 h 1, . . . 2 hh and 308 in eachlevel is also same and its logic and circuit are shown in FIG. 5. Theembodiment 510 is the circuit implementation of one block 2 h 0 and theembodiment 520 is the circuit implementation of both block 201 and block2 hh in FIG. 2 a together. The operation principle of 510 is: 1) all theinput A0 to A7 are set to zero as in embodiment 400 in FIG. 4. 2) Setthe gate input 522 of P transistor 501 to zero to pre-charge the node503 to Vdd , then turn 522 to Vdd and turn off the P transistor 501before the signal A0 to A7 arrive. If all the input A0 to A7 are zero,the input of N transistors are zero and all the N transistors 502 areOFF and the node 503 is kept in Vdd and the output signal of inverter504 is zero. If only one input among A0 to A7 is Vdd and all the othersare zero, which is the worst case, the delay of 510 is that one Ntransistor discharge the drain parasitic capacitance of the eight samesize N transistor down to ground plus the delay of one inverter.

The binary encoding logic and circuit is shown as embodiment 600 in FIG.6. The operation principle of 600 is: 1) all the input h₀, h₂, h₄ and h₆are set zero. 2) Set the gate input 611 of P transistor 601 to zero topre-charge the node 603 to Vdd, then turn 611 to Vdd and turn off the Ptransistor 601 before the signal h₀, h₂, h₄ and h₆ arrive. If all theinput signal h₀, h₂, h₄ and h₆ are zero, the input of N transistors arezero and all the N transistors 602 are OFF and the node 603 is kept inVdd and the output signal of inverter 604 is zero. If only one inputamong h₀, h₂, h₄ and h₆ is Vdd and all the others are zero, which is theworst case, the delay of 600 is that one N transistor discharging thedrain parasitic capacitance of the four same size N transistor down toground plus the delay of one inverter.

The MUX logic and circuit is shown in FIG. 7 as embodiment 700. Theoperation principle of 700 is: 1) the input signal Ph₀, Ph₁, Ph₂, Ph₃,Ph₄, Ph₅, Ph₆ and Ph₇ are set zero. 2) Set the gate input 705 of Ptransistor 701 to zero to pre-charge the node 703 to Vdd, then turn 705to Vdd and turn off the P transistor 701 before the signal Ph₀, Ph₁,Ph₂, Ph₃, Ph₄, Ph₅, Ph₆ and Ph₇ arrive. Since Ph₀, Ph₁, Ph₂, Ph₃, Ph₄,Ph₅, Ph₆ and Ph₇ are from Priority encoding, only one signal among themis Vdd and all the other are zero if there is hit. After AND logic, onlyone output of the seven AND gate 708 is equal to the input value whichis the selected bit from Ba₀ to Ba₇. If the selected bit from Ba₀ to Ba₇is zero, the node 703 is kept Vdd and the output of inverter 704 is zeroand the selected bit value zero is passed out. If the selected bit fromBa₀ to Ba₇ is Vdd, one N transistor among eight N transistor 702 isturned ON and the node 703 is discharged down to ground and the outputof inverter 704 is Vdd(logical one) and the selected bit value Vdd ispassed out, which is the worst case, the delay of 700 is one Ntransistor discharging the drain parasitic capacitance of the eight samesize N transistor down to ground plus the delay of one inverter and oneAND gate. Usually one AND gate includes one inverter and one NAND gate,so the delay of 700 is one N transistor discharging the drain parasiticcapacitance of the eight same size N transistor down to the ground plusthe delay of two inverter and one NAND gate.

The entire Priority encoding logic and circuit are simplified as a fourbasic building block of 400, 510, 600 and 700 in FIGS. 4, 5, 6 and 7.The delay of each block 400, 510, 600 and 700 are comparable and we callthe time of delay of each block 400, 510, 600 and 700 one stage. If wedefine the delay of hit logic block 510 as T_(h), one inverter delay isT_(i) and one NAND gate delay is T_(n). The delay of priority encodingblock 400 is (T_(h)+T_(n)) since the delay of block 400 is one more NANDgate delay comparing with block 510. The delay of block 600 is roughlyT_(h). The delay of MUX block 700 is (T_(h)+T_(n)+T_(i)). The extradelay of each higher level priority encoding is a MUX 700 selectiondelay because that the Hit signal in each priority encoding level isgenerated one stage earlier than the binary hit address and theselection signal of the MUX is already available when the binary addressto be selected arrive and will not suffer extra delay.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

1. A content addressable memory(CAM) device, comprising: a few sub-blockCAM; a priority encoding logic among the HIT or MISS (comparison result)of each row within the sub-block CAM; a priority encoding logic amongthe sub-block CAM; and a priority encoding logic among the HIT or MISSof each row.
 2. A CAM according to claim 1, wherein sub-block aredivided into four quadruple.
 3. A CAM according to claim 2, wherein thesub-blocks in each quadruple are arranged as a matrix.
 4. A CAMaccording to claim 1, further comprising: A priority encoding logicamong the HIT results of a sub-group rows within a sub-block CAM; and apriority encoding logic among the sub-group rows within a sub-block CAM.5. A priority encoding logic among the HIT or MISS of each row of a CAMdevice, comprising: a hierarchal multi-level priority encoding logic. 6.A priority encoding logic according to claim 5, further comprising: afirst level priority encoding logic among the HIT or MISS of a few rowas a first level group.
 7. A priority encoding logic according to claim6, further comprising: a first level group HIT or MISS generationthrough an AND logic among the HIT or MISS of each row within a firstlevel group.
 8. A priority encoding logic according to claim 6, furthercomprising: a first level priority binary address generation of apriority HIT address within a first level group.
 9. A priority encodinglogic according to claim 5 and claim 7, further comprising: a secondlevel priority encoding logic among the first level group HIT or MISS ofa few first level group.
 10. A priority encoding logic according toclaim 5 and claim 9, further comprising: a second level priority binaryaddress generation of a priority first level group HIT within a secondlevel group.
 11. A priority encoding logic according to claim 10,further comprising: a second level group HIT or MISS generation throughan AND logic among each first level group HIT or MISS within each secondlevel group.
 12. A priority encoding logic according to claim 5, furthercomprising: a third level priority encoding logic among the second levelgroup HIT or MISS of a few second level group.
 13. A priority encodinglogic according to claim 5 and claim 12, further comprising: a thirdlevel priority binary address generation of a priority third level groupHIT within a third level group.
 14. A priority encoding logic accordingto claim 12, further comprising: a third level group HIT or MISSgeneration through an AND logic among each second level group HIT orMISS within each third level group.
 15. A priority encoding logicaccording to claim 8, claim 10 and claim 13, further comprising: a thirdlevel binary priority HIT address through combining first level binarypriority address, second level binary priority address and third levelbinary priority address.